AI-assisted chip verification/debugging tool that reads simulation waveforms, traces failures to RTL, proposes fixes with trade-offs and reruns the customer simulator to show waveform diffs.
Product sources: hardware intelligence official Wave product + Y Combinator S26 company page
Wave is a terminal-native waveform debugger for chip verification with an AI verification agent built into the viewer. It reads VCD and FST waveforms, lets engineers ask why a signal failed, traces values back through the simulation, proposes alternative RTL fixes with trade-offs, reruns the customer's simulator and shows the resulting waveform diff.
AiToolMap did not provide Wave with an RTL design, inspect its proposed fixes or reproduce simulator runs. The fixed 50-source panel found no eligible exact-product review or benchmark. Hardware Intelligence's separate WaveZip product has published compression/overhead measurements, but those concern waveform storage and are not transferred to Wave's debugging score. The 7.8 rating is LOW-confidence and not rank eligible.
A wrong RTL fix can create expensive downstream failures, so agent suggestions should remain subordinate to deterministic simulation, formal verification and human review. Wave's all-local execution, customer-controlled model endpoint and evidence-linked reasoning are strong trust features. Teams should still isolate write permissions, review generated RTL changes and require their normal verification/sign-off process before accepting fixes. 1 2
Wave is unusually well matched to its target workflow. It runs fully on the customer's machines, works over SSH/tmux, uses the customer's own model key or internal endpoint and keeps design data inside the customer's network. Agent answers are pinned to concrete signals and ticks rather than presented only as natural-language conclusions. The strongest design choice is verification of a proposed fix through the customer's existing simulator: the agent does not merely suggest code, it reruns the failing test and displays the changed waveform. That creates an auditable engineering loop.
Wave is still a pilot product. Hardware Intelligence was founded in 2026, YC lists a two-person team, and public access remains demo/waitlist driven with no numeric pricing. The vendor positions the product against expensive incumbent EDA tools, but there is no independent evidence here establishing debug-time savings, root-cause accuracy or robustness across different simulators and large proprietary designs. Current native file support is VCD/FST; FSDB integration is described as something the team will wire up with customers.
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